1. Field of the Invention
The present invention relates to a data processing apparatus and method for performing register renaming without additional registers, which can be applied in a variety of situations, for example in relation to security sensitive applications.
2. Description of the Prior Art
It is known to provide a data processing apparatus which performs data processing operations in response to data processing instructions that reference logical registers (also known as program model registers), whilst the data processing apparatus itself stores the data values which are subjected to those data processing operations in a set of physical registers. Rather than maintaining a fixed mapping between the logical registers and the physical registers, it is known to carry out a technique known as register renaming in which the mapping between logical registers and physical registers is varied and updated.
The register renaming may be performed for predominately performance related reasons, such as to allow parallelism in the execution of data processing instructions, for example when data processing instructions in a sequence are executed either in parallel or at least out of order and register renaming techniques are then used to maintain different versions of a given logical register, such that those data processing instructions may be executed in this parallel or out-of-order fashion without data hazards occurring. Whilst register renaming is advantageous in terms of the performance benefits it can bring, the additional hardware which must be provided in a data processing apparatus to allow such register renaming to occur is a disadvantage due to the cost and complexity which it introduces. This drawback makes the opportunities to use register renaming techniques in relatively small, low-cost, low-power devices particularly limited.
Register renaming is also known as a valuable technique in the context of security sensitive devices because of the manner in which this technique makes it more difficult for an attacker to externally derive information about the internal operation of such a data processing apparatus, for example by fine-grained observation of the power consumption of the device or by invasive techniques which seek to introduce values into particular registers in order to observe the effect this has on the operation of the device. Whilst it would be desirable to allow the benefits of register renaming to be applied to such security sensitive devices, such devices are often constructed as small, low-cost, low-power devices and hence the additional architectural requirements associated with typical register renaming techniques have traditionally limited the opportunities for applying register renaming techniques in this context. For example, many known register renaming techniques require the number of physical registers to exceed the number of logical registers in order to enable those register renaming techniques to operate, and hence for any particular design of device, more physical registers would be required to support register renaming than would be required if register renaming was not used. In small devices, such as a small secure microprocessor, the size of the register file containing the physical registers is significant, and the resultant increase in the size of the register file required often precludes use of many register renaming techniques within such devices.
The paper “Instruction Stream Mutation for Non-Deterministic Processors”, Irwin, Page and Smart, Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP'02), 2002, describes various techniques that can be used to guard against differential power analysis (DPA) security attacks, one of the techniques involving a register renaming technique (referred to the article as register remapping) that uses a “liveness table” to control register renaming. In accordance with this technique, the number of physical registers does not need to exceed the number of logical registers, but extra instructions have to be added into the instruction flow to produce the information required to maintain the liveness table. Accordingly such an approach will require modification to the code executing on the device, and will have a significant impact on performance due to the need to execute those additional instructions.
It would be desirable to provide an improved technique for allowing the benefits of register renaming to be applied to data processing apparatuses, in particular in the context of small, low cost, low power devices, which alleviates the additional hardware requirement associated with many register renaming techniques, whilst avoiding the need to add additional instructions into the instruction flow.